1. Field of the Invention
The present invention relates, generally, to semiconductor memory devices, and particularly to semiconductor memory devices capable of correct reading of stored data under a variable supply voltage. The invention is particularly applicable to nonvolatile semiconductor memories such as flash EEPROMs.
2. Description of the Background Art
In recent years, semiconductor memory devices have been used in various electronic equipments. Particularly, programmable EPROMs capable of erasing data, EEPROMs and flash EEPROMs have been known as nonvolatile semiconductor memories having floating gates. The flash EEPROM is one of a flash erasing type memory (i.e., is operable to electrically and simultaneously erase all bits of stored data), and can program the data byte by byte. Further, one memory transistor forms one memory cell, which enables high integration on a semiconductor substrate.
Many small electronic equipments using semiconductor memories are powered not only by external power supplies but also by internal power supplies, i.e., batteries. The power can be supplied selectively from the external power supplies and internal power supplies
Generally, externally supplied power has a stable voltage level, but an output voltage of a battery decreases as a discharging time elapses In other words, when the power is supplied by the battery, the supply voltage is variable Although the invention is generally applicable to various semiconductor memories, an example, in which the invention is applied to a flash EEPROM, will be described hereinafter.
FIG. 9 is a block diagram showing a background of the invention, and particularly showing a flash EEPROM. Referring to FIG. 9, an EEPROM 200 includes a memory cell array 1 provided with a large number of memory cells MC arranged in rows and columns, a row decoder 2 for selectively activating word lines Xl-Xm, a column decoder 3a for selecting a memory block (or region) to be accessed, a column decoder 3b for selecting a bit line to be accessed in the memory block, a sense amplifier 5 for amplifying a data signal, and an output buffer 6 for supplying output data D.sub.0. Although the circuit block for reading the data is shown in FIG. 9, it should be noted that flash EEPROM 200 comprises a circuit block for writing the data, not shown.
In the reading operation, row decoder 2 decodes an externally applied row address signal (not shown) to activate selectively one of word lines Xl-Xm. Memory cell MC connected to the activated word line grounds bit lines BLl-BLn in accordance with the stored data signal Each memory cell MC is turned on or off in response to the stored data signal. Therefore, potentials of bit lines BLl-BLn are brought to a ground potential or a floating state in accordance with the data stored in the memory cell accessed by row decoder 2.
Column decoder 3a supplies block selecting signals YAl-YAi in response to an externally applied column address signal (not shown). NMOS transistors 6l-6i for selecting the blocks are selectively turned on in response to block selecting signals YAl-YAi, respectively. Column decoder 3b decodes the externally applied column address signal (not shown) to supply column selecting signals YBl-YBn. NMOS transistors 9l-9n for selecting the column are selectively turned on in response to column selecting signals YBl-YBn, respectively.
Therefore, the potential of one bit line selected by column decoder 3b, i.e., the read data signal is transmitted from the memory block selected by column decoder 3a to sense amplifier 5. Sense amplifier 5 amplifies the transmitted data signal, and the amplified data signal is supplied as output data D.sub.0 from output buffer 6.
FIG. 10 is a circuit diagram of sense amplifier 5 shown in FIG. 9. Referring to FIG. 10, sense amplifier 5 includes PMOS transistors 21, 22 and 23 as well as NMOS transistors 24, 25 and 26. Transistors 21, 22 and 23 have their gates grounded. Transistor 24 has a gate connected to a signal line 27. Transistors 22 and 25 are connected in series between power supply potential Vcc and signal line 27. Transistors 23 and 26 are connected in series between supply potential Vcc and signal line 27. Signal line 27 corresponds to signal line 27 shown in FIG. 9. Amplified signal SA.sub.5 is supplied through a common connection node of transistors 23 and 26.
Then, an operation of sense amplifier 5 for reading the data will be described below. First, a case will be described in which the data stored in the memory cell MC designated by row decoder 2 and column decoders 3a and 3b is "1". It is also assumed that the memory transistor forming the memory cell MC is turned on in this case. Therefore, the potential at input node N3 in sense amplifier 5 lowers, and thus transistor 24 is turned off. Thereby, the potential at node N2 rises, so that transistors 25 and 26 are turned on. Owing to the turn-on of transistors 25 and 26, the potential of node N3 is maintained at a level which is not very low. Consequently, amplified signal SA.sub.5 at the low level is supplied through output node N1.
In the foregoing operation, it is noted that transistor 25 operates to prevent excessive lowering of the potential of input node N3. If the potential of input node N3 is excessively lowered, the rising of the potential of the bit line would be delayed when the data signal at the inverted level (i.e., the high level in the above case) were read in the next read cycle. Therefore, it is noted that transistor 25 contributes to reduce the time required for reading the data.
When the memory cell MC designated by row decoder 2 and column decoders 3a and 3b stores "0", the designated memory cell MC is turned off. Therefore, the potential of input node N3 in sense amplifier 5 has the high level, and thus transistor 24 is turned on. Thereby, the potential of node N2 has the low level, and thus transistors 25 and 26 are turned off. Consequently, excessive increase of the potential of input node N3 is prevented. In this case, amplified signal SA.sub.5 at the high level is supplied through output node N1.
FIG. 11 is a diagram showing transition of an output voltage of sense amplifier 5 under variable supply voltage Vcc. Referring to FIG. 11, the abscissa represents the change of the supply voltage Vcc and the ordinate represents the change of the output voltage of sense amplifier 5. Referring to FIG. 11, when the data read from the memory cell is "0", sense amplifier 5 supplies the output voltage indicated by line SA.sub.50. When the memory cell stores the data of "1", sense amplifier 5 supplies the output voltage indicated by line SA.sub.51. As shown in FIG. 11, output voltage SA.sub.50 for the data of "0" and output voltage SA.sub.51 for the data of "1" changes as the supply voltage Vcc changes.
Further, line Vth in FIG. 11 indicates the change of threshold voltage of a circuit at the succeeding stage (e.g., output buffer 6 shown in FIG. 9) connected to the output of the sense amplifier 5. Line Vth indicates the threshold voltage of a circuit such as an inverter, which receives the output voltage of sense amplifier 5.
Flash EEPROM 200 is designed to operate properly under the fixed supply voltage Vcc. Specifically, sense amplifier 5 is designed to correctly sense the data signal supplied from the memory cell under the fixed supply voltage, e.g., Vcc of 5 V. In other words, conventional sense amplifier 5 supplies output data signals SA.sub.50 and SA.sub.51 suitable to threshold voltage Vth of the circuit connected in the succeeding stage when the fixed supply voltage (Vcc=5 V) is supplied.
Accordingly, when the electronic equipment receives the supply voltage from the battery, i.e., internal power supply, the output voltage of the battery gradually reduces as the discharging time of the battery elapses. This means that the supply voltage Vcc supplied to the semiconductor memory gradually reduces. As can be understood from FIG. 11, output voltages SA.sub.50 and SA.sub.51 of sense amplifier 5 and threshold constant voltage Vth of the circuit at the succeeding stage are designed to be optimum under the supply voltage Vcc of 5 V supplied thereto. In other words, they are designed to perform the correct data reading operation under the supply voltage of 5 V. Due to the lowering of supply voltage Vcc, a relation between output voltages SA.sub.50 and SA.sub.51 of sense amplifier 5 and threshold constant voltage Vth of the circuit in the succeeding stage changes in a direction indicated by an arrow AR in FIG. 11, so that the optimum relationship for the data reading is destroyed. Particularly, in a case that supply voltage Vcc lowers approximately below 3 V, all output voltages SA.sub.50 and SA.sub.51 exceed threshold voltage Vth. This means that all data is read as "0" under such supply voltage Vcc. In other words, lowering of supply voltage Vcc causes error in the data reading operation.
In order to avoid the above problems, there may be additionally provided other semiconductor memories which are provided with sense amplifiers having the optimum sensing characteristics under the supply voltage Vcc of 3 V. However, this increases the number of semiconductor devices used in the small electronic equipment, which is not preferred in view of the space and cost.